EETimes.com - 3-D memristor chip debuts

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PORTLAND, Ore. ? Memristors technology got a boost recently from Hewlett-Packard Labs, which described the first 3-D memristor chip at a conference in Berkeley, Calif.

The Memristor and Memristive Systems Symposium was co-sponsored by the University of California, the Semiconductor Industry Association and the National Science Foundation. HP Labs (Palo Alto, Calif.) provided details of a prototype chip designed by HP researcher Qiangfei Xia that stacked memristor crossbar memory cells on top of a CMOS logic chip.

"Xia used imprint lithography to add a memristor crossbar on top of a CMOS logic circuit," said HP Labs Fellow Stan Williams, inventor of HP's memristive memory technology. "He has built an integrated hybrid circuit with both transistors and memristors." Williams and HP colleague Greg Snider previously proposed an FPGA in which configuration bits were located above CMOS transistors in a memristor

PORTLAND, Ore. ? Memristors technology got a boost recently from Hewlett-Packard Labs, which described the first 3-D memristor chip at a conference in Berkeley, Calif.

The Memristor and Memristive Systems Symposium was co-sponsored by the University of California, the Semiconductor Industry Association and the National Science Foundation. HP Labs (Palo Alto, Calif.) provided details of a prototype chip designed by HP researcher Qiangfei Xia that stacked memristor crossbar memory cells on top of a CMOS logic chip.

"Xia used imprint lithography to add a memristor crossbar on top of a CMOS logic circuit," said HP Labs Fellow Stan Williams, inventor of HP's memristive memory technology. "He has built an integrated hybrid circuit with both transistors and memristors." Williams and HP colleague Greg Snider previously proposed an FPGA in which configuration bits were located above CMOS transistors in a memristor

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